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a42l8316 series preliminary 256k x 16 cmos dynamic ram with edo page mode preliminary (november, 2002, version 0.2) amic technology, corp . document title 256k x 16 cmos dynamic ram with edo page mode revision history rev. no. history issue date remark 0.0 initial issue january 26, 1999 preliminary 0.1 modify ac data august 20, 2002 0.2 delete the - 30 grade november 1, 2002
a42l8316 series preliminary 256k x 16 cmos dynamic ram with edo page mode preliminary (november, 2002, version 0.2) 1 amic technology, corp . features n organization: 262,144 words x 16 bits n part identification - a42l8316 (512 ref.) n single 3.3v power supply/built - in vbb generator n low power consumption - operating: 105ma ( - 35 max) - standby: 2.5ma (ttl), 1.5ma (cmos) 1.0ma (self - refresh current) n high speed - 35/40 ns ras access time - 17/18 ns column address access time - 10/11 ns cas access time - 16/18 ns edo page mode cycle time n industrial operating temperature range: - 40 c to 85 c for - u n fast page mo de with extended data out n separate cas ( ucas , lcas ) for byte selection n 512 refresh cycle in 8ms n read - modify - write, ras - only, cas - before - ras , hidden refresh capability n ttl - compatible, three - state i/o n jedec standard packages - 400mil, 40 - pin soj - 400mil, 40/44 tsop type ii package general description the a42l8316 is a new generation randomly accessed memory for graphics, organized in a 262,1 44 - word by 16 - bit configuration. this product can execute byte write and byte read operation via two cas pins. the a42l8316 offers an accelerated fast page mode pin configuration n n soj n n tsop vcc i/o 0 i/o 1 nc a1 a2 a3 vcc a4 a5 a6 a7 a8 i/o 13 i/o 14 i/o 15 vss a42l8316s 21 we ras i/o 12 oe i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 0 nc nc vcc vss ucas lcas nc i/o 8 i/o 9 i/o 10 i/o 11 vss 20 19 18 12 16 17 13 14 15 11 10 9 8 7 6 5 4 3 2 1 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vcc i/o 0 i/o 1 nc a1 a2 a3 a4 a5 a6 a7 a8 i/o 13 i/o 14 i/o 15 vss a42l8316v 23 we ras i/o 12 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 0 nc nc vcc vss ucas lcas nc i/o 8 i/o 9 i/o 10 i/o 11 vss 22 21 20 14 18 19 15 16 17 13 10 9 8 7 6 5 4 3 2 1 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 43 44 vcc oe cycle wit h a feature called extended data out (edo). this allow random access of up to 512 words within a row at a 62/55 mhz edo cycle, making the a42l8316 ideally suited for graphics, digital signal processing and high performance computing systems. pin descrip tions symbol description a0 ? a8 address inputs i/o 0 - i/o 15 data input/output ras row address strobe lcas column address strobe for lower byte (i/o 0 ? i/o 7 ) ucas column address strobe for uppe r byte (i/o 8 ? i/o 15 ) we write enable oe output enable vcc 3.3v power supply vss ground nc no connection
a42l8316 series p reliminary (november, 2002, version 0.2) 2 amic technology, corp . selection guide symbol description - 35 - 40 unit t rac maximum ras access ti me 35 40 ns t aa maximum column address access time 17 18 ns t cac maximum cas access time 10 11 ns t oea maximum output enable ( oe ) access time 10 11 ns t rc minimum read or write cycle time 62 70 ns t pc minimum e do cycle time 16 18 ns functional description the a42l8316 reads and writes data by multiplexing an 18 - bit address into a 9 - bit row and 9 - bit column address. ras and cas are used to strobe the row address and the column address, respectively. the a42l8316 has two cas inputs: lcas controls i/o 0 - i/o 7 , and ucas controls i/o 8 - i/o 15 , ucas and lcas function in an identical manner to cas in that either will generate an internal cas signal. the cas function and timing are determined by the first cas ( ucas or lcas ) to transition low and by the last to transition high. byte read and byte write are controlled by using lcas and ucas separately. a read cycle is performed by holding the we signal high during ras / cas operation. a write cycle is executed by holding the we signal low during ras / cas operation; the input data is latched by the falling edge of we or cas , whichever occurs later. the data inputs and outputs are routed through 16 common i/o pins, with ras , cas , we and oe controlling the in direction. edo page mode operation all 512 columns within a selected row to be randomly accessed at a high data rate. a edo page mode cycle is initiated with a row address latched by ras followed by a column address latched by cas . while holding ras low, cas can be toggled to strobe changing column addresses, thus achieving shorter cycle times. the a42l8316 offers an accelerated fast page mode cycle through a feature ca lled extended data out, which keeps the output drivers on during the cas precharge time (t cp ). since data can be output after cas goes high, the user is not required to wait for valid data to appear before starting t he next access cycle. data - out will remain valid as long as ras and oe are low, and we is high; this is the only characteristic which differentiates extended data out operation from a standard r ead or fast page read. a memory cycle is terminated by returning both ras and cas high. memory cell data will retain its correct state by maintaining power and accessing all 512 combinations of the 9 - bit row address es, regardless of sequence, at least once every 8ms through any ras cycle (read, write) or ras refresh cycle ( ras - only, cbr, or hidden). the cbr refresh cycle automatically controls the row addres ses by invoking the refresh counter and controller. power - on the initial application of the vcc supply requires a 200 s wait followed by a minimum of any eight initialization cycles containing a ras clock. during power - on, the vcc cu rrent is dependent on the input levels of ras and cas . it is recommended that ras and cas track with vcc or be held at a valid v ih during power - on to avoid current surges.
a42l8316 series p reliminary (november, 2002, version 0.2) 3 amic technology, corp . bl ock diagram recommended operating conditions (ta = 0 c to +70 c or - 40 c to +85 c) symbol description min. typ. max. unit notes vcc power supply 3.0 3.3 3.6 v 1 vss input high voltage 0.0 0.0 0.0 v 1 v ih input high voltage 2.0 - vcc + 0.3 v 1 v il input low voltage - 0.5 - 0.8 v 1 vss vcc cas clock generator column address buffers refresh counter & controller row address buffers ras clock generator we clock generator row decoder oe clock generator ay0 - ay8 ax0 - ax8 sense amplifiers column decoders data i/o buffers memory array 512 x 512 x 16 . . . 512 . . . . . 512 x 16 . . i/o 0 to i/o 15 oe we ucas lcas a0 - a8 ras
a42l8316 series preliminary (november, 2002, version 0.2) 4 amic technology, corp . truth table function ras ucas lcas we oe address i/os notes standby h h h x x x high - z read: word l l l h l row/col. data out read: lower byte l h l h l row/col. i/o 0 - 7 = data out i/o 8 - 15 = high - z read: upper byte l l h h l row/col. i/o 0 - 7 = high - z i/o 8 - 15 = data out write: word l l l l h row/col. data in write: lower byte l h l l h row/col. i/o 0 - 7 = data in i/o 8 - 15 = x write: upper byte l l h l h row/col. i/o 0 - 7 = x i/o 8 - 15 = data in read - write l l l h ? l l ? h row/col. data out ? data in 1,2 edo - page - mode read: hi - z - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l h h h ? l h ? l row/col. col. data out data out 2 2 edo - page - mode write - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l l l h h row/col. col. data in data in 1 1 edo - page - mode read - write - first cycle - subsequent cycles l l h ? l h ? l h ? l h ? l h ? l h ? l l ? h l ? h row/col. col. data out ? data in data out ? data in 1, 2 1, 2 hidden refresh read l ? h ? l l l h l row/col. data out 2 hidden refresh write l ? h ? l l l l x row/col. data in ? high - z 1 ras - only refresh l h h x x row high - z cbr refresh h ? l l l x x x high - z 3 self refresh h ? l l l h x x high - z note: 1. byte write may be executed with either ucas or lcas active. 2. byte read may be executed with either ucas or lcas active. 3. only one cas signal ( ucas or lcas ) must be active.
a42l8316 series p reliminary (november, 2002, version 0.2) 5 amic technology, corp . absolute maximum ratings* input voltage (vin) . . . . . . . . . . . . . . . . . . . - 0.5v to + 4.6v output voltage (vout) . . . . . . . . . . . . . . . . - 0.5v to +4.6v power supply voltage (vcc) . . . . . . . . . . - 0.5v to +4.6v operating temperature (t opr ) . . . . . . . . . . 0 c to +70 c storage temperature (t stg ) . . . . . . . . . - 55 c to +150 c soldering temperature x time (t solder ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c x 10sec power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . 1w short circuit output curre nt (iout) . . . . . . . . . . . . . 50ma latch - up current . . . . . . . . . . . . . . . . . . . . . . . . . . 200ma *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress rating s only. functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may af fect device reliability. dc electrical characteristics (vcc = 3.3v 0.3v, vss = 0v, ta = 0 c to +70 c or - 40 c to +85 c) - 35 - 40 unit test conditions notes symbol parameter min. max. min. max. i il input leakage current - 5 +5 - 5 +5 m a 0v vin vcc pins not under test = 0v i ol output leakage current - 5 +5 - 5 +5 m a d out disabled, 0v vout vcc i cc1 operating power supply current - 105 - 100 ma ras , ucas , lcas and address cycling; t rc = min. 1, 2 i cc2 ttl supply current supply current - 2.5 - 2.5 ma ras = ucas = lcas = v ih i cc3 average power supply current, ras refresh mode - 105 - 100 ma ras and address cycling, ucas = lcas = v ih , t rc = min. 1 i cc4 edo page mode average power supply current - 105 - 100 ma ras and address = v il , ucas , lcas and address cycling; t pc = min. 1, 2 i cc5 cas - before - ras refresh power supply current - 105 - 100 ma ras and ucas or lcas cycling; t rc = min. 1 i cc6 cmos standby power supply current - 1.5 - 1.5 ma ras = ucas = lcas = vcc - 0.2v i cc7 self refresh mode current - 1.0 - 1.0 ma ras = cas vss+0.2v all other input high levels are vcc - 0.2v or input low levels are vss +0.2v v oh 2.4 - 2.4 - v i out = - 2.0ma v ol output voltage - 0.4 - 0.4 v i out = 2.0ma
a42l8316 series preliminary (november, 2002, version 0.2) 6 amic technology, corp . ac characteristics (vcc = 3.3v 0.3v, vss = 0v, ta = 0 c to +70 c or - 40 c to +85 c) test conditions: input timi ng reference level: v ih /v il =2.0v/0.8v output reference level: v oh /v ol =2.0v/0.8v output load: 2ttl gate + cl (50pf) assumed t t =2ns - 35 - 40 # std symbol parameter min. max. min. max. unit notes t t transition time (rise and fall) 1 50 1 50 ns 4, 5 1 t rc random read or write cycle time 62 - 70 - ns 2 t rp ras precharge time 23 - 26 - ns 3 t ras ras pulse width 35 10k 40 10k ns 4 t cas cas pulse width 6 10k 7 10k ns 5 t rcd ras to cas delay time 10 25 10 29 ns 6 6 t rad ras to column address delay time 8 18 8 22 ns 7 7 t rsh cas to ras hold time 6 - 7 - ns 8 t csh cas h old time 31 - 33 - ns 9 t crp cas to ras precharge time 5 - 5 - ns 10 t asr row address setup time 0 - 0 - ns 11 t rah row address hold time 6 - 7 - ns 12 t clz cas to output in low z 3 - 3 - ns 8 13 t rac access time from ras - 35 - 40 ns 6,7 14 t cac access time from cas - 10 - 11 ns 6, 13 15 t aa access time from column address - 17 - 18 ns 7, 13 16 t oea oe access time - 10 - 11 ns 17 t ar column address hold time from ras 31 - 36 - ns 18 t rcs read command setup time 0 - 0 - ns 19 t rch read command hold time 0 - 0 - ns 9 20 t rrh read command hold time reference to ras 0 - 0 - ns 9
a42l8316 series preliminary (november, 2002, version 0.2) 7 amic technology, corp . ac characteristics (continued) (vcc = 3.3v 0.3v, vss = 0v, ta = 0 c to +70 c or - 40 c to +85 c) test conditions: input timing reference level: v ih /v il =2.0v/0.8v output reference level: v oh /v ol =2.0v/0.8v output load: 2ttl gate + cl (50pf) assumed t t =2ns - 35 - 40 # std symbol parameter min. max. min. max. unit notes 21 t ral column address to ras lead time 17 - 18 - ns 22 t coh output hold after cas low 3 - 3 - ns 23 t off output buffer turn - off delay time - 3 - 3 ns 8, 10 24 t asc column address setup time 0 - 0 - ns 25 t cah column address hold time 6 - 7 - ns 26 t oes oe low to cas high set up 7 - 8 - ns 27 t wcs write command setup time 0 - 0 - ns 11 28 t wch w rite command hold time 6 - 7 - ns 11 29 t wcr write command hold time to ras 31 - 36 - ns 30 t wp write command pulse width 6 - 7 - ns 31 t rwl write command to ras lead time 10 - 11 - ns 32 t cwl write command to cas lead time 7 - 7 - ns 33 t ds data - in setup time 0 - 0 - ns 12 34 t dh data - in hold time 6 - 7 - ns 12 35 t dhr data - in hold time to ras 31 - 36 - ns 36 t rwc read - modify - write cycle time 85 - 95 - ns 37 t rwd ras to we delay time (read - modify - write) 46 - 52 - ns 11 38 t cwd cas to we delay time (read - modify - write) 21 - 23 - ns 11 39 t awd column address to we delay time (read - modify - write) 28 - 30 - ns 11
a42l8316 series preliminary (november, 2002, version 0.2) 8 amic technology, corp . ac characteristics (continued) (vcc = 3.3v 0.3v, vss = 0v, ta = 0 c to +70 c or - 40 c to +85 c) test conditions: input timing reference level: v ih /v il =2.0v/0.8v output reference level: v oh /v ol =2.0 v/0.8v output load: 2ttl gate + cl (50pf) assumed t t =2ns - 35 - 40 # std symbol parameter min. max. min. max. unit notes 40 t oeh oe hold time from we 6 - 7 - ns 41 t oep oe high puls e width 5 - 5 - ns 42 t pc read or write cycle time (edo page) 16 - 18 - ns 14 43 t cpa access time from cas precharge (edo page) - 18 - 20 ns 13 44 t cp cas precharge time 6 - 7 - ns 45 t pcm edo page mode rmw cyc le time 40 - 43 - ns 46 t crw edo page mode cas pulse width (rmw) 30 - 32 - ns 47 t rasp ras pulse width (edo page) 35 200k 40 200k ns 48 t csr cas setup time ( cas - before - ras ) 5 - 5 - ns 3 49 t chr cas hold time ( cas - before - ras ) 10 - 10 - ns 3 50 t rpc ras to cas precharge time 10 - 10 - ns 3 51 t oez output buffer turn - off delay from oe - 3 - 3 ns 8 52 t rass ras pulse width ( c - b - r self refresh) 100 - 100 - m s 53 t rps ras precharge time ( c - b - r self refresh) 62 - 70 - ns 54 t chs cas hold time ( c - b - r self refresh) - 50 - - 50 - ns
a42l8316 series preliminary (november, 2002, version 0.2) 9 amic technology, corp . notes: 1. i cc1 , i cc3 , i cc4 , and i cc5 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. specified values are obtained with the outputs open. 3. an initial pause of 200 m s is required after power - up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas - before - ras initialization cycles instead of 8 ras cycles are required. 8 initi alization cycles are required after extended periods of bias without clocks. 4. ac characteristics assume t t = 2ns. all ac parameters are measured with a load equivalent to two ttl loads and 50pf, v il (min.) 3 gnd and v ih (max.) vcc. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6. operation within the t rcd (max.) limit insures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. i f t rcd is greater than the specified t rcd (max.) limit, then access time is controlled exclusively by t cac . 7. operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is great er than the specified t rad (max.) limit, then access time is controlled exclusively by t aa . 8. assumes three state test load (5pf and a 500 w thevenin equivalent). 9. either t rch or t rrh must be satisfied for a read cycle. 10. t off (max.) defines the time a t which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. t wcs , t wch , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. i f t wcs 3 t wcs (min.) and t wch 3 t wch (min.), the cycle is an early write cycle and data - out pins will remain open circuit, high impedance, throughout the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read - modify - write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. these parameters are referenced to ucas and lcas leading edge in early write cycles and to we leading edge in read - modify - write cycles. 13. access time is determined by the longer of t aa or t cac or t cpa . 14. t asc 3 t cp to achieve t pc (min.) and t cpa (max.) values.
a42l8316 series preliminary (november, 2002, version 0.2) 10 amic technology, corp . word read cycle t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(21) t rch(19) t rrh(20) t ar(17) t rcs(18) t oea(16) t rac(13) t aa(15) t cac(14) t clz(12) t oez(51) t off(23) high-z : high or low valid data-out row address column address i/o 0 ~ i/o 15 oe we a0~a8 ucas lcas ras
a42l8316 series preliminary (november, 2002, version 0.2) 11 amic technology, corp . word write cycle (early write) t ras(3) t rp(2) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t rah(11) t asc(24) t cah(25) t rad(6) t ral(21) t wch(28) : high or low row address column address i/o 0 ~ i/o 15 oe a0~a8 ucas lcas ras t ar(17) t cwl(32) t rwl(31) t wp(30) t wcs(27) valid data-in t ds(33) t dh(34) we t wcr(29) t dhr(35)
a42l8316 series preliminary (november, 2002, version 0.2) 12 amic technology, corp . word write cycle ( late write) t ras(3) t rp(2 ) t rc(1) t crp(9) t csh(8) t rcd(5) t rsh(7) t cas(4) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) t ral(21) row address column address a0~a8 ucas lcas ras t ar(17 ) t cwl(32) t rwl(31) t wp(30) t rah(11) t oeh(40) t ds(33) t dh(34) i/o 0 ~ i/o 15 : high or low oe we high-z vaild data-in t wcr(29) t dhr(35)
a42l8316 series preliminary (november, 2002, version 0.2) 13 amic technology, corp . word read - modify - write cycle t ras(3) t rp(2) t rwc(36) t crp(9) t csh(8) t rcd(5) t rsh(7) t asr(10) t crp(9) t rah(11) t cah(25) t rad(6) row address column address a0~a8 ucas lcas ras t ar(17) t rwl(31) t asc(24) t cwl(32) t awd(39) t cwd(38) t rwd(37) t wp(30) t oea(16) t oez(51) t clz(12) t cac(14) t aa(15) t rac(13) t ds(33) t dh(34) high-z data-out data-in : high or low i/o 0 ~ i/o 15 oe we t oeh(40) t rcs(18)
a42l8316 series preliminary (november, 2002, version 0.2) 14 amic technology, corp . edo page mode word read cycle t rasp(47) t rp(2) ras ucas lcas t cas(4) t cas(4) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t ar(16) t ral(21) a0~a8 oe we i/o 0 ~ i/o 15 : high or low t asc(24) t cp(44) t csh(8) t asc(24) t cah(25) t cah(25) row column column column t rch(19) t rcs(18) t rcs(18) t rch(25) t rcs(18) t cah(25) t rrh(20) t off(23) t oez(51) t aa(15) t oea(16) t oep(41) t cac(14) t clz(12) t oez(51) t cpa(43) t oes(26) t aa(15) t oea(16) t coh (22) t cac(14) t rac(13) t cac(14) t clz(12) data-out data-out data-out
a42l8316 series preliminary (november, 2002, version 0.2) 15 amic technology, corp . edo page mode early word write cycle t rasp(47) t rp(2) ras ucas lcas t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t rcd(5) t csh(8) t crp(9) t crp(9) t pc(42) t rsh(7) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t cah(25) t asc(24) t ral(21) row column column a0~a8 we t cwl(32) t wch(28) t wcs(27) t wcs(27) column t cwl(32) t wch(28) t wcs(27) t wch(28) t cwl(32) t rwl(31) t wp(30) t wp(30) t wp(30) t dh(34) t ds(33) t dh(34) t ds(33) t ds(33) t dh(34) data-in data-in data-in i/o 0 ~ i/o 15 oe : high or low
a42l8316 series preliminary (november, 2002, version 0.2) 16 amic technology, corp . edo page mode word read - modify - write cycle t rasp(47) ras t crw(46) t cp(44) t crw(46) t cp(44) t crw(46) t rcd(5) t csh(8) t crp(9) t crp(9) t pcm(45) t rsh(7) t rp(2) t asr(10) t rah(11) t rad(6) t asc(24) t cah(25) t asc(24) t cah(25) t asc(24) t cah(25) t ral(21) t rcs(18) t cwd(38) t rwd(37) t cwl(32) t cwd(38) t cwl(32) t cwd(38) t cwl(32) t rwl(31) t oea(16) t oea(16) t oea(16) t wp(30) t wp(30) t wp(30) t awd(39) t awd(39) t awd(39) t cac(14) t aa(15) t rac(13) t oez(51) t ds(33) t aa(15) t cpa(43) t dh(34) t oez(51) t ds(33) t dh(34) t oez(51) t ds(33) t dh(34) t aa(15) t cpa(43) t clz(12) t clz(12) t clz(12) high-z : high or low i/o 0 ~ i/o 15 oe we a0~a8 ucas lcas data-out data-in data-out data-in data-out data-in row column column column t oeh(40)
a42l8316 series preliminary (november, 2002, version 0.2) 17 amic technology, corp . ras only refresh cycle cas before ras refresh cycle t ras(3) t rp(2) t rc(1) ras t crp(9) t rpc(50) t asr(10) t rah(11) a0~a8 ucas : high or low row note: we, oe = don't care. lcas t ras(3) t rp(2) t rc(1) ras t rp(2) t rpc(50) t cp(44) t csr(48) t chr(49) t off(23) i/o 0 ~ i/o 15 ucas high-z : high or low note: we, oe, address = don't care. lcas
a42l8316 series preliminary (november, 2002, version 0.2) 18 amic technology, corp . hidden refresh cycle (word read) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(17) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) a0~a8 ucas ras t rah(11) t rrh(20) t rcs(18) i/o 0 ~ i/o 15 : high or low oe high-z t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(21) t cac(14) t off(23) t aa(15) t clz(12) t rac(13) we row column valid data-out lcas t oez(51) t oea(16)
a42l8316 series preliminary (november, 2002, version 0.2) 19 amic technology, corp . hidden refresh cycle (early word write) t ras(3) t rp(2 ) t rc(1) t crp(9) t ar(17) t rcd(5) t asr(10) t crp(9) t asc(24) t cah(25) t rad(6) a0~a8 ras t rah(11) : high or low oe t ras(3) t rp(2 ) t chr(49) t rc(1) t rsh(7) t ral(21) we row column t wcs(27) t wch(28) t wp(30) t ds(33) t dh(34) valid data-in i/o 0 ~ i/o 15 ucas lcas
a42l8316 series preliminary (november, 2002, version 0.2) 20 amic technology, corp . edo page mode read - early - write cyc le (pseudo read - modify - write) ras : high or low i/o 0 ~ i/o 15 oe we a0~a8 ucas t rp(2) t rasp(47) t crp(9) t csh(8) t rcd(5) t cas(4) t cp(44) t cas(4) t cp(44) t cas(4) t cpr(9) t rsh(7) t pc(42) t pc(42) row column column t ral(21) t cah(25) t asc(24) t cah(25) t asc(24) t cah(25) t asc(24) t asr(10) t rah(11) t rad(6) column t rcs(18) t rch(19) t wcs(27) t wch(28) data-out data-out data-in t dh(34) t ds(33) t aa(15) t cap(43) t cac(14) t coh(22) t aa(15) t rac(13) t cac(14) t oea(16) lcas
a42l8316 series preliminary (november, 2002, version 0.2) 21 amic technology, corp . self refresh mode n self refresh mode. a. entering the self refresh mode: the a42l8316 self refresh mode is entered by using cas before ras cycle and holding ras and cas signal ?low? longer than 100 m s. b. continuing the self refresh mode: the self refresh mode is continued by holding ras ?low? after entering the self refresh mode. it does not depend on cas being ?high? or ?low? after entering the self refresh mode continue the self refresh mode. c. exiting the self refresh mode: the a42l8316 exits the self refresh mode when the ras signal is brought ?high?. t rass(52) t rp(2) t crp(9) t csr(48) t rpc(50) ras t rps(53) t chs(54) t asr(10) t cp(44) t off(23) a0~a8 : high or low high-z i/o 0 ~ i/o 15 ucas lcas row col note: we, oe = don't care.
a42l8316 series preliminary (november, 2002, version 0.2) 22 amic technology, corp . capacitance (f = 1mhz, ta = roo m temperature, vcc = 3.3v 0.3v) symbol signals parameter max. unit test conditions c in1 a0 - a8 5 pf vin = 0v c in2 ras , ucas , lcas , we , oe input capacita nce 7 pf vin = 0v c i/o i/o 0 - i/o 15 i/o capacitance 7 pf vin = vout = 0v ordering codes package ras access time 35ns 40ns self - refresh soj 40l (400mil) a42l8316s - 35 a42l8316s - 40 yes tsop 40/44 l type ii (400mil) a42l8316v - 35 a42l8 316v - 40 yes tsop 40/44 l type ii (400mil) a42l8316v - 35u a42l8316v - 40u yes note: - u is for industrial operating temperature range.
a42l8316 series preliminary (november, 2002, version 0.2) 23 amic technology, corp . package information soj 40l (400mil) outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol m in nom max min nom max a - - 0.144 - - 3.66 a 1 0.025 - - 0.64 - - a 2 0.105 0.110 0.115 2.67 2.79 2.92 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.022 0.41 0.46 0.56 c 0.008 0.010 0.014 0.20 0.25 0.36 d 1.020 1.025 1.030 25.91 26.04 26.16 e 0.395 0.400 0.405 10.03 10.16 10.29 e 0.044 0.050 0.056 1.12 1.27 1.42 e 1 0.355 0.366 0.376 9.114 9.383 9.652 h e 0.430 0.440 0.450 10.92 11.18 11.43 l 0.081 0.093 0.105 2.083 2.39 2.70 s - - 0.050 - - 1.27 y - - 0.004 - - 0.10 q 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash. 1 e h e 20 21 40 a 1 a 2 e e 1 c s d seating plane d y l 1 a b b q
a42l8316 series preliminary (november, 2002, version 0.2) 24 amic technology, corp . package inf ormation tsop 40/44l (type ii) (400mil) outline dimensions unit: inches/mm 1 e h e l 1 l 1 c 44 a 1 a 2 a s d y e d b l l q dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.013 0.015 0.017 0.32 0.37 0.42 c 0.003 0.005 0.009 0.08 0.13 0.23 d 0.720 0.725 0.730 18.28 18.41 18.54 e 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 bsc 0.80 bsc h e 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0. 60 l 1 - 0.031 - - 0.80 - s - - 0.035 - - 0.90 y - - 0.004 - - 0.10 q 1 3 5 1 3 5 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.

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